1. Field
The present disclosure relates to nanostructures and programmable electronic devices incorporating nanostructures, e.g., nanoelectronic devices incorporated into a circuit.
2. Background Information
“Top-down” approaches to increasing electronic device density are known. An alternative “bottom-up” technological approach uses functional nano-structures assembled from chemically synthesized, nano-scale building blocks. Wide-scale integration of functional nano-scale devices involves connecting nanoscale electrically conducting wires to microscale electrodes. One approach to address this connectivity issue is the simultaneous lateral growth of a high density of highly oriented, metal catalyzed silicon nanowires on a patterned substrate where the nanowires are between two vertical sidewalls.
Known attempts to program the conductivity of a device element have used charge storage in an isolated region to control the conduction in a nearby semiconducting region (EEPROM or Flash memory) or have changed the structure of the material between two states, such as amorphous and crystalline, with each state having a different conductivity. The EEPROM involves fabrication of a double-gated structure and uses high voltage for programming; supplying these voltages externally can involve additional power supplies. Generating the voltages on-chip from lower supply voltages can involve substantial additional circuitry; in addition these memories can be difficult to scale to nanoscale dimensions. Phase-change materials can involve complex combinations of elements, some of which may be toxic, and control of the composition can be difficult.